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. A major challenge in the area of hardware verification isto devise methods that can handle circuits of practical size. This paperintends to show how the applicability of combinational circuit verificationtools based on binary decision diagrams (BDDs) can be greatly improved.The introduction of dynamic variable ordering techniques already makesthese tools more robust; a designer no longer needs to worry about agood initial variable order. In addition, we present a novel approach...

Exploiting structural similarities in a BDD-based verification method