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Our approach for verifying the equivalence of two VHDL architectures consists in translating these descriptions into functional forms and then in proving the equivalence of these functions. As far as replicated or parallel architectures are concerned, an induction-based method is used for verifying generic n-bit descriptions. This technique takes advantage of the regular structure of these devices and can give better results than the BDD-based approaches. However, induction requires complete specifications, whereas the designers usually supply partial specifications. Therefore, we propose a specialized automatic method for generalizing such incomplete statements, before the Boyer-Moore proof process.

An automatic generalization method for the inductive proof of replicated and parallel architectures