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The major goal of this paper is to clarify how large and practical sequential machines can be verified with the current most powerful supercomputers. The basic algorithm used is an implicit symbolic model checking algorithm, which is shown to be 100 times and 40 times more efficient in time and space than the conventional symbolic model checking algorithms. Based on the algorithm, a vectorized symbolic model checking algorithm, which is suitable for execution on vector processors, is also proposed. Some benchmark results show that it achieves about 6  20 acceleration ratio and it can verify a 16 bit pipelined ALU with 4 word register file, which supports 16 arithmetic/logical operations, in around 12 minutes on a vector processor HITAC S-820/80.

Vectorized symbolic model checking of computation tree logic for sequential machine verification