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With the advance in hardware integration, system-on-a-chip (SoC) test activities using only automatic test equipments (ATEs) result in an expensive option. Hardware-based test may reduce the ATE dependency. However, hardware-based test imposes some constraints like area overhead and processing speed degradation. The main objective of this work is to investigate and evaluate a less intrusive test approach called software-based test. Software-based test uses an embedded processor as source and sink of the test, sending the test patterns and reading the responses. A new integrated design and test environment has been developed to automatically synthesize test programs to test non-programmable cores of SoCs. Some benchmarks ISCAS85 and ISCAS89 are used to evaluate the proposed methodology.

Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures